1. Field of the Invention
The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) device in which p- and n-type thin film transistors are formed, a method of fabricating the CMOS device, an image display apparatus including the CMOS device, and a method of manufacturing the image display apparatus.
2. Description of the Related Art
Recently, with the progress of crystallization technologies using excimer lasers and the like, a liquid crystal display integrated with a peripheral driving circuit that includes thin film transistors (TFTs) using a polysilicon film by a low-temperature process (hereinafter called low-temperature polysilicon film) is emerging to the forefront of the technology. Such a peripheral driving circuit includes a CMOS transistor device as a main component comprising p- and n-type thin film transistors (hereinafter called p-type TFT and n-type TFT, respectively) for achieving a high performance and a low power consumption. Hereinafter, such a CMOS transistor device will be called CMOS-TFT.
Like a CMOS-type single-crystal large scale integrated circuit (hereinafter called single-crystal LSI), setting the threshold voltage (Vth) is one most important subject of a CMOS-TFT. A non-doped polycrystalline silicon is usually used as an active semiconductor layer of such a CMOS-TFT. The threshold voltage, therefore, can be easily set in theory by adjusting the charge amount in a gate insulating film and the interface charge density between the active semiconductor layer and the gate insulating film. In practice, however, the CMOS-TFT having a non-doped active semiconductor layer is extremely difficult to set the threshold voltage by adjustment of the interface charge density, for the reasons explained below.
(1) A gate insulating film of a thin film transistor is a deposited film formed by, e.g., plasma CVD (Chemical Vapor Deposition) and hence does not have such a good bulk characteristic as that of a thermal oxide film. As a result, fixed charges are necessarily produced in the gate insulating film. For example, in a silicon oxide film (SiO2 film) formed by SiH4—N2O plasma CVD, SiH4 and N2O molecules which have not been sufficiently decomposed, form positive fixed charges, and consequently, the flat band voltage shifts in the negative direction. This flat band voltage is an important reference value for evaluating the interface between an active semiconductor layer and a gate insulating film and for evaluating the gate insulating film. The larger the shift from a theoretical value is, the worse the evaluation result is.
(2) An insulating film formed by, e.g., plasma CVD or low-pressure CVD does not have such a superior Si/SiO2 interface characteristic as that of a thermal oxide film. So, charges pertaining to the interface level cause a shift of the flat band voltage. In particular, in a thin film transistor using a glass substrate, a clean interface is difficult to obtain because a strongly acidic or strongly alkaline substrate cleaner cannot be used.
(3) Like the interface level, the grain boundary level in a polysilicon film can shift the flat band voltage by capturing or releasing carriers. In particular, impurities such as carbon (C), nitrogen (N), and oxygen (O) contained in the polysilicon film (especially in a grain boundary) may have some influence on the flat band voltage.
For any of the above reasons, the threshold voltages (i.e., the Id-Vg characteristics) of both p- and n-type TFTs of a CMOS-TFT using a non-doped polysilicon film often shift about 1 to 2 V in the negative direction. Although these threshold voltages can be shifted to a certain degree in the positive direction by optimizing the film formation conditions of a gate insulating film, they cannot be controlled to arbitrary values desired. In addition, the range of adjustment is narrow. For solving these problems, a method of controlling the threshold voltages by doping each channel region of a CMOS-TFT with impurities has been proposed.
More specifically, when an amorphous silicon film as an initial state of an active semiconductor layer is formed by plasma CVD, a few ppm to ten-odd ppm (gas ratio) of B2H6 gas containing p-type impurities is added together with reaction gas (SiH4) and diluent gas (H2). The added B2H6 gas is decomposed by plasma discharge and incorporated into the amorphous silicon film. The advantage of this method is that the entire amorphous silicon film (both p- and n-type TFTs) can be doped with the impurities without adding any process.
This method is extensively used as a preferable threshold voltage adjustment method in the fabrication of single-crystal LSIs. But, because a mass separation type ion implanter capable of processing large-area substrates such as substrates of liquid crystal displays is still in course of development, an ion-doping apparatus using a non-mass separation type ion source (e.g., an RF plasma ion source) is generally used. That is, an RF plasma ion source is used to add impurities (dopant) at a predetermined concentration to the channel region of a p- or n-type TFT so that the threshold voltage (flat band voltage) is adjusted with the dose of the impurities.
As will be described below, however, the accuracy required in the threshold voltage control of a CMOS-TFT is far severer than that required in a single-crystal LSI, and so no satisfactory control can be obtained by conventional control methods.
Prior to explaining the reasons why the threshold voltage control of the CMOS-TFT requires such high accuracy, the characteristic features of the CMOS-TFT and a peripheral circuit configuration using the CMOS-TFT will be described below.
First, the size of the peripheral circuit using the CMOS-TFT is large.
The mobility of a CMOS-TFT (particularly a CMOS-TFT having a low-temperature polysilicon film) is 30 to 150 (cm2/Vs). This value is low as about {fraction (1/20)} to ⅕ the mobility of a MOS transistor in a single-crystal LSI. To obtain an equivalent driving force, therefore, it is necessary to increase the device size (channel width) at substantially the same ratio. Besides, in a liquid crystal display including CMOS-TFTs, both of signal lines and scan lines are long, so the wiring resistance and stray capacitance are high. Hence, the load on the peripheral circuit is far larger than that of a single-crystal LSI.
As one practical example of the peripheral circuit of a liquid crystal display, a gate driving circuit of a liquid crystal display will be described below. This gate driving circuit includes a plurality of inverter stages in order to increase the driving power of the CMOS-TFT step by step. The channel width increase ratio of a stage to the next stage is about 1:3, and the channel width of the final output stage is about 1.5 mm. Accordingly, the total of the channel widths of all CMOS-TFTs per bit reaches a few mm.
Second, the power-supply voltage of the peripheral circuit of a liquid crystal display is far higher than that of a single-crystal LSI.
While a representative power-supply voltage of the single-crystal LSI is 3.3 (V), the driving voltage of a gate driving circuit corresponding to a 5 V-driven liquid crystal is approximately 16 (V). Besides, both of the S value and the absolute value of the threshold voltage of a CMOS-TFT are large. This is another cause of the high power-supply voltage.
On the basis of the aforementioned intrinsic characteristic features of a CMOS-TFT, the reasons why the threshold voltage control of the CMOS-TFT requires high accuracy will be described below.
Either of an input signal and an output signal changes with the width of a power-supply voltage (Vdd) between its low level “L” (ground potential GND) and high level “H” (power-supply voltage Vdd) (see, e.g., FIG. 16). When the input signal level is “L”, a p-type TFT is switched on into its conductive state and an n-type TFT is switched off, so the output signal level goes “H”. Conversely, when the input signal level is “H”, the n-type TFT is switched on and the p-type TFT is switched off, so the output signal level goes “L”. If the threshold voltage (i.e., the Id-Vg curve) of the n-type TFT shifts to the negative side, this n-type TFT is not completely switched off when the input signal level is “L”. Consequently, a leakage current called tunneling current flows in the order of a node at Vdd, (power-supply potential), the p-type TFT, the n-type TFT and a node at GND (ground potential).
This tunneling current is equal to a drain current I0 (hereinafter called zero current) when Vg=0 (V) on the Id-Vg curve of the n-type TFT. As the threshold voltage shifts to the negative side, the zero current increases. Similarly, if the threshold voltage of the p-type TFT shifts to the positive side, a tunneling current flows due to the zero current of the p-type TFT when the input signal level is “H”.
As described above, the tunneling current greatly increases the power consumption of the CMOS-TFT. In the aforementioned gate driving circuit, the static power consumption by the tunneling current can reach several tens of mW or more for 1 (nA/μm) per unit channel width.
Due to the above-described first and second characteristic features of the CMOS-TFT, the power consumption of the whole peripheral circuit significantly increases if the threshold voltage shifts even slightly. Besides, a large tunneling current causes serious defects or obstacles such as a decrease in the signal amplitude, local heat generation, and progressive deterioration of the TFT characteristics.
As described above, unlike in a single-crystal LSI, in a CMOS-TFT, the tunneling current produces a fatal damage and it is necessary to set the threshold voltage with high accuracy to prevent the tunneling current. By the aforementioned conventional threshold voltage control method using ion-doping, however, no such high accuracy can be obtained and so satisfactory results are difficult to obtain. More specifically, this is due to the following features of the conventional threshold voltage control method.
(1) Ion implantation of p-type impurities changes the whole of an active semiconductor layer into a weak p-type semiconductor. The threshold voltages of both n- and p-type TFTs shift to the positive side accordingly. In principle, it is impossible separately to set them. It is therefore obvious that the threshold voltage of the CMOS-TFT is difficult to optimize by the conventional method. Besides, it is impossible greatly to reduce the tunneling current in the CMOS-TFT by the conventional method, in principle.
(2) In the conventional method, if an amorphous silicon film is excessively doped with p-type impurities before crystallization, the crystal grain size may decrease in case of laser crystallization, or, in case of thermal crystallization (SPC) nucleation and crystal growth may become difficult to develop and so crystallinity may degrade.
(3) When an RF plasma ion source is used, doping at a low dose (approximately 5×1012 (/cm2) or less) with a small ion current required is extremely difficult because the ion current density is high. Besides, the use of the RF ion source increases the number of parameters (e.g., RF power, pressure, and conditions of electrodes and chamber inner walls) on ion current. This method is therefore inferior in stability and reproducibility of ion species or ion current.
(4) The activation ratio of impurities is low in a low-temperature fabrication process using a glass substrate. In particular, when the dose to the channel region is relatively high, ion damages are difficult to repair, and activation becomes insufficient. A channel-doping step using a lower dose is desired therefore. But, an ion-doping apparatus using a conventional RF plasma ion source cannot well perform doping at a low dose. Besides, to optimize the threshold voltage of a CMOS-TFT by selectively doping, photolithography must usually be performed twice or more. This complicates the fabrication process.